1. Field of the Invention
The present invention relates to a semiconductor device such as a flash memory, an EEPROM (Electrically Erasable Programmable Read Only Memory), or the like and a method of manufacturing such a semiconductor device, and more particularly to a structure of a capacitive element of a booster circuit included in a semiconductor device and a method of manufacturing such a structure.
2. Description of the Related Art
Nonvolatile semiconductor memory devices such as flash memories, EEPROMs, etc. which are generally known in the art have a cell structure comprising, on a semiconductor substrate, source and drain diffused regions, a floating gate electrode disposed on a channel region between the source and drain diffused regions with a gate insulating film interposed therebetween, and a control gate electrode disposed on the floating gate electrode with an insulating film interposed therebetween. The assignee of the present invention has proposed a process of manufacturing such a nonvolatile semiconductor memory by forming an element dividing trench in self-alignment with the floating gate electrode, as disclosed in Japanese patent Laid-open publication No. 7-22195 (JP, 7-022195, B). The disclosed process, which is also called an FSA process, is advantageous in that the floating gate electrode can be localized only on the channel region between the source and drain diffused regions and an area taken up by a memory cell can be minimized.
For writing and erasing data, the nonvolatile semiconductor memories such as flash memories and EEPROMs require positive and negative voltages which are greater than the power supply voltage that is supplied to the semiconductor memory device. The power supply voltage supplied from an external circuit to a nonvolatile semiconductor memory is normally 3 V, 3.3 V, or 5 V, whereas the nonvolatile semiconductor memory requires a greater voltage of −11 V and +12 V for erasing data and a greater voltage of −11 V or in the range from +5 to +9 V for writing data. It is general practice to generate these voltages so that they are greater than the power supply voltage within the semiconductor memory device by increasing the power supply voltage, which is supplied from an external circuit, with a charge pump circuit (i.e., booster circuit) included in the semiconductor memory device. The charge pump circuit comprises a capacitive element (i.e., capacitor), a switching element, and a diode in combination. The capacitive element typically has a capacitance of about 1500 pF. The capacitive element is fabricated in the nonvolatile semiconductor memory within an ordinary semiconductor device fabrication process. Japanese laid-open patent publication No. 2000-49499 (JP, P2000-049499A) discloses a charge pump circuit for simultaneously generating positive and negative potentials, which is applicable as a flash memory.
To the capacitive element of the charge pump circuit, there is applied a voltage which is much higher than the voltage that can normally be applied between the floating gate electrode and the channel region and which is higher than the power supply voltage supplied to the nonvolatile semiconductor memory device. Therefore, this capacitive element needs to have a lower electrode on a relatively thick insulating film and an upper electrode thereon with an insulating film as a capacitive layer being interposed therebetween. If a nonvolatile semiconductor memory is to be produced according to the FSA process disclosed in JP7-022195B, since a lower electrode of a capacitive element cannot be formed on a thin gate oxide film, it is necessary to form the lower electrode on a trench-embedded insulating film, thus providing a capacitive element for a charge pump circuit.
FIGS. 1A and 1B show in cross section the arrangement of a nonvolatile semiconductor memory device incorporating a capacitive element. FIG. 1A shows a memory cell area and FIG. 1B shows an area where a capacitive element of a charge pump circuit is formed. Specifically, FIG. 1A shows a cross section along a plane including a channel region of the memory cell area, the plane being perpendicular to a straight line interconnecting a source region and a drain region.
Trench-embedded insulators 101 are formed in the surface of semiconductor substrate 100. In the capacitive element, lower electrode 102 made of polysilicon (polycrystalline silicon) is formed on trench-embedded insulators 101, and upper electrode 104 is formed over lower electrode l02, with insulating film 103 interposed therebetween. Interlayer insulating film 105 is disposed so as to cover lower electrode 102 and upper electrode 104. Interlayer insulating film 105 is connected to insulating film 103. Interconnection contacts 106, 107 extend through interlayer insulating film 105 are electrically connected to lower electrode 102 and upper electrode 104, respectively. Upper electrode 104 is of a double-layer structure including polysilicon layer 111 disposed closer to lower electrode 102 and silicide layer 112 disposed on polysilicon layer 111.
In the memory cell area, a plurality of floating gate electrodes 109 of polysilicon are disposed over a channel region between adjacent trench-embedded insulators 101 with gate insulating film 108 interposed therebetween. Control gate electrode 113 is formed over floating gate electrodes 109 with insulating film (i.e., intergate insulating film) 110 interposed therebetween. Control gate electrode 113 is fabricated in the same process as upper electrode 104 of the capacitive element area. Like upper electrode 104, control gate electrode 113 is of a double-layer structure including polysilicon layer 111 and silicide layer 112. Control gate electrode 113 is covered with interlayer insulating film 105.
In the case where the capacitive element of the charge pump circuit is to be formed on the trench-embedded insulating films for device isolation, lower electrode 102 of the capacitive element and the floating gate electrodes 109 of the memory cell cannot be fabricated in one process, and a separate photolithographic process is needed for forming the lower electrode. Specifically, after trenches are formed in self-alignment with floating gate electrodes 109 and insulators are embedded in the trenches for device isolation, the upper surface of trench-embedded insulators 101 is patterned to form lower electrode 102. The above process poses limitations on the layout in the nonvolatile semiconductor memory device.
Since the capacitance of the capacitive element for the charge pump circuit is relatively large, it is necessary to form excessively large trench regions for the purpose of device isolation, and it is also necessary to divide the lower electrode and position the divided regions separately in association with the respective trench regions for device isolation. If the large trench regions are formed, then the chip as the semiconductor memory device has a large area, and when the surface of the trench-embedded insulators is planarized by chemical mechanical polishing (CMP), dents tend to be formed substantially centrally in the trench-embedded insulators, adversely affecting the shape of the capacitive element formed thereon and making it difficult to produce a highly accurate capacitance.